
// include spi_register_asyn_syn, spi_register_asyn

module spi_register_asyn_syn
(	data_in,
	data_out,
	we,
	clk,
	rst,
	rst_syn
);

parameter WIDTH = 8;			// width of the register 
parameter RESET_VALUE = 0;		// reset value of the register

input  [WIDTH-1 : 0] data_in;
output [WIDTH-1 : 0] data_out;
input  				 we;
input  				 clk;
input		         rst;
input		         rst_syn;

reg	   [WIDTH-1 : 0] data_out;


always @ (posedge clk , posedge rst )
begin
  if(rst)
	 data_out <= #1 RESET_VALUE;
  else if (rst_syn)
  	 data_out <= #1 RESET_VALUE;
  else if (we)
  	 data_out <= #1 data_in;
end

endmodule

module spi_register_asyn
(	data_in,
	data_out,
	we,
	clk,
	rst
);

parameter WIDTH = 8;			// width of the register 
parameter RESET_VALUE = 0;		// reset value of the register

input  [WIDTH-1 : 0] data_in;
output [WIDTH-1 : 0] data_out;
input  				 we;
input  				 clk;
input		         rst;

reg	   [WIDTH-1 : 0] data_out;


always @ (posedge clk , posedge rst )
begin
  if(rst)
	 data_out <= #1 RESET_VALUE;
  else if (we)
  	 data_out <= #1 data_in;
end

endmodule

